2.4GHz Type-II ∆Σ Fractional-N PLL for Bluetooth

Confidentiality Notice

This is an active research project. Due to ongoing publication process (targeting MIXDES 2026 International Conference, submission scheduled for March 2026) and intellectual property considerations, detailed circuit design, specifications, and simulation results cannot be publicly disclosed at this time. Repository and comprehensive documentation will be made public following publication.

Project Overview

Historic Milestone: Sri Lanka's First RFIC Tapeout

This is a groundbreaking group RFIC design project that represents Sri Lanka's first radio frequency integrated circuit design for fabrication. The project, which began in May 2025, involves designing a 2.4GHz Type-II ∆Σ Fractional-N Phase-Locked Loop (PLL) synthesizer for Bluetooth Low Energy (BLE) applications using the IHP SG13G2 PDK (130nm SiGe BiCMOS) technology.

PDK Transition: SKY130 to IHP SG13G2

Initially, the project targeted the SkyWater SKY130 PDK. However, we encountered critical inductor size constraint issues and timing challenges specific to the SKY130 process that made it unsuitable for our 2.4 GHz fractional-N PLL design requirements. After thorough analysis, the team made the strategic decision to switch to the IHP SG13G2 130nm SiGe BiCMOS PDK, which offers superior RF performance, better inductor Q-factors, and more suitable metal stack characteristics for high-frequency PLL design.

My Specific Role: Inductor Design & Characterization Lead

Within the group, I am solely responsible for:

• Complete Inductor Design Workflow: Developing comprehensive on-chip inductor design methodology encompassing full-wave EM simulation (Ansys HFSS 3D Layout), S-parameter extraction, SPICE model generation with parasitic R-L-C networks, and integration with team's charge pump and VCO architectures
• Electromagnetic Simulation & Optimization: Full-wave 3D EM simulation using HFSS 3D Layout with IHP SG13G2 layer stackup specifications, parametric optimization of inductor geometries for maximum Q-factor at 2.4 GHz
• Novel PVT Analysis (Primary Research Contribution): Investigating Process-Voltage-Temperature variations impact on inductor performance and PLL locking capability. Demonstrating design robustness and lock maintenance despite metal thickness variations across fabrication process corners
• Team Deliverables: Providing optimized layout geometries, broadband S-parameter datasets (DC-20+ GHz), validated SPICE subcircuit models, frequency-dependent quality factor characterization, and comprehensive parasitic extraction for accurate PLL loop dynamics and phase noise prediction

Publication Target

This work is being prepared for submission to MIXDES 2026 International Conference (Mixed Design of Integrated Circuits and Systems), with submission scheduled for March 2026. The conference focuses on mixed-signal and RF IC design, making it an ideal venue for presenting Sri Lanka's first RFIC tapeout and our novel PVT analysis methodology.

Project Scope (General Information)

While detailed circuit specifications are confidential pending publication, the general project scope includes:

• Technology Node: IHP SG13G2 130nm SiGe BiCMOS process (switch from SKY130 due to inductor constraints)
• Application: 2.4GHz Type-II ΔΣ Fractional-N PLL synthesizer for Bluetooth Low Energy (BLE)
• Target Frequency: 2.4 GHz carrier generation with fractional frequency resolution
• Architecture: Type-II Delta-Sigma Fractional-N Phase-Locked Loop with charge pump and LC-VCO
• Design Methodology: Full-custom analog/RF IC design with comprehensive PVT analysis
• Passive Components: Custom-designed on-chip spiral inductors optimized for high Q-factor at 2.4 GHz
• My Contribution: Complete inductor design workflow, EM simulation, S-parameter extraction, SPICE modeling, and PVT analysis
• Design Tools: Ansys HFSS 3D Layout (EM simulation), Cadence Virtuoso (schematic/layout), IHP PDK design kit
• Publication: Targeting MIXDES 2026 Conference (submission March 2026)
• Timeline: May 2025 - Present, with repository and documentation public release following publication

Current Work: RF Inductor Design for Fractional-N PLL

My current focus is on developing a complete inductor design workflow for the 2.4 GHz PLL using Ansys HFSS 3D Layout with IHP SG13G2 PDK. This involves:

IHP SG13G2 PDK Layer Stackup Integration

The IHP SG13G2 130nm SiGe BiCMOS process offers superior RF performance compared to standard CMOS, with multiple metal layers specifically optimized for high-frequency passive components. Accurate 3D modeling of the complete layer stackup in HFSS is critical for realistic inductor performance predictions at 2.4 GHz:

• Metal Stack: Modeling all metal layers (ThinMet, Metal1-Metal5, TopMetal1-TopMetal2) with IHP-specific thicknesses and spacing rules
• Substrate Modeling: Silicon substrate with SiGe BiCMOS-specific doping profiles, thickness, and frequency-dependent loss tangent at 2.4 GHz
• Via Structures: IHP PDK-compliant inter-layer vias for connecting inductor turns and implementing center-tap configurations
• Optimized Metal Selection: Using top thick metal layers (TopMetal1/TopMetal2) for lowest series resistance and maximum Q-factor

Inductor Performance Optimization for 2.4 GHz PLL

Key parameters being optimized through parametric HFSS sweeps for fractional-N PLL application:

• Quality Factor (Q) at 2.4 GHz: Target Q > 15 for low phase noise VCO performance, achieved through geometry optimization
• Inductance Value: Designing inductors in 1-5 nH range for LC-VCO tank circuits at 2.4 GHz
• Self-Resonant Frequency (SRF): Ensuring SRF > 6 GHz to maintain inductive behavior with minimal capacitive parasitic effects
• Series Resistance: Minimizing metal loss through optimal trace width and leveraging IHP's thick top metal layers
• Substrate Coupling: Analyzing and mitigating eddy current losses specific to BiCMOS substrate characteristics
• PLL Integration: Designing inductor footprints compatible with charge pump and divider circuitry placement

Novel PVT Analysis: Process-Voltage-Temperature Variations

Primary Research Contribution: Investigating the impact of fabrication process variations on inductor performance and PLL locking behavior:

• Process Corners: Analyzing metal thickness variations (TT, FF, SS corners) across IHP fabrication tolerances
• Temperature Sweep: Characterizing inductor Q-factor and resistance from -40°C to +125°C for automotive-grade reliability
• Voltage Variations: Evaluating substrate loss sensitivity to supply voltage fluctuations in charge pump operation
• PLL Lock Robustness: Demonstrating that PLL maintains stable lock despite inductor parameter shifts across PVT corners
• Design Margins: Establishing safety margins for inductor specifications to ensure yield and manufacturability

Design Variables & Trade-offs

Design Workflow & Methodology

1. HFSS 3D Layout Electromagnetic Simulation Setup

Creating accurate inductor models in HFSS 3D Layout for IHP SG13G2 130nm SiGe BiCMOS:

• Import IHP PDK Stackup: Define all metal and dielectric layers with exact IHP SG13G2 specifications (including ThinMet, Metal1-5, TopMetal1-2 with BiCMOS-optimized thicknesses)
• Geometry Creation: Draw spiral inductor patterns with parametric variables (turns, width, spacing, diameter) optimized for 2.4 GHz operation
• Port Definition: Lumped port excitation at inductor terminals for accurate S-parameter extraction
• Boundary Conditions: Radiation boundary (air box) with size optimization for 2.4 GHz wavelength
• Mesh Generation: Adaptive mesh refinement with focus on high-current-density regions and metal edges
• Frequency Sweep: Broadband S-parameter simulation from DC to 20 GHz to capture SRF, Q-peak, and parasitic resonances

2. Inductor Performance Extraction for PLL Application

Post-processing HFSS results to extract key inductor metrics for fractional-N PLL design:

• Inductance (L) at 2.4 GHz: Extracted from Im(Z₁₁) = 2πfL, targeting 1-5 nH range for LC-VCO
• Quality Factor (Q) at 2.4 GHz: Q = Im(Z₁₁) / Re(Z₁₁) = ωL / R_series, target Q > 15 for low phase noise
• Series Resistance (R_s): Real part of input impedance including skin effect, substrate loss, and metal resistance
• Self-Resonant Frequency: Frequency where Im(Z₁₁) = 0, ensuring SRF > 6 GHz for 2.4 GHz operation
• S-Parameter Export: Full 2-port S-parameters for integration with VCO and charge pump models

3. SPICE Model Generation with Parasitic Networks

Converting HFSS EM simulation results into circuit-level SPICE models:

• π-Model Extraction: Fitting HFSS Z-parameters to equivalent R-L-C π-network for circuit simulation
• Parasitic Capacitance: Extracting inter-turn capacitance and substrate capacitance from S-parameters
• Frequency-Dependent Models: Creating broadband SPICE models valid from 100 MHz to 10 GHz
• PVT Corner Models: Generating separate SPICE models for TT, FF, SS process corners and temperature extremes

4. Novel PVT Analysis Methodology (Research Contribution)

Primary research contribution investigating Process-Voltage-Temperature variations:

• Process Corner Simulation: Re-running HFSS with metal thickness variations (±10% typical, ±20% worst-case) representing IHP fabrication process corners (TT/FF/SS)
• Temperature-Dependent Loss: Modeling substrate conductivity and metal resistivity changes from -40°C to +125°C
• PLL Locking Analysis: Verifying that inductor L and Q variations across PVT corners do not prevent PLL from achieving lock at 2.4 GHz with acceptable phase noise
• Design Margin Validation: Demonstrating robustness through Monte Carlo simulations with inductor parameter distributions derived from PVT analysis
• Yield Optimization: Identifying optimal inductor geometry that maximizes fabrication yield while meeting PLL performance specifications across all corners

5. Integration with PLL Circuit Design Team

Providing comprehensive inductor models and documentation to teammates designing VCO, charge pump, and divider blocks:

• S-Parameter Datasets: Exported Touchstone (.s2p) files for direct import into Cadence Virtuoso ADE
• SPICE Subcircuit Models: Validated π-models with PVT corner variants for transient and AC simulations
• Performance Tables: Documenting L, Q, SRF, R_s vs. frequency and temperature for design reference
• Layout Footprint & Guidelines: GDS-II layout templates with clearance zones, ground return paths, and shielding recommendations
• Phase Noise Contribution: Calculating inductor Q-factor impact on VCO phase noise for system-level budgeting

Tools & Technologies

Project Timeline & Status

• ✅ May 2025 - Project Initiation: Assembled team for Sri Lanka's First RFIC Tapeout targeting Bluetooth PLL
• ✅ PDK Selection & Transition: Initially selected SKY130, but switched to IHP SG13G2 due to inductor size constraints and timing issues
• ✅ IHP SG13G2 Stackup Setup: Complete BiCMOS layer stackup modeled in HFSS with accurate material properties and metal stack
• 🔄 Inductor Design & Optimization: Parametric sweeps, Q-factor optimization at 2.4 GHz, and geometry refinement (Current Phase)
• 🔄 PVT Analysis (Novel Contribution): Process-Voltage-Temperature variation analysis for inductor performance and PLL lock robustness (In Progress)
• 🔄 SPICE Model Generation: Developing broadband SPICE models with parasitic R-L-C networks for circuit integration (In Progress)
• ⏳ Full PLL Integration: Integration of inductor models with team's VCO, charge pump, and divider blocks (Upcoming)
• ⏳ Post-Layout Simulation: Full PLL simulation with extracted parasitics for phase noise and locking analysis (Planned)
• ⏳ MIXDES 2026 Submission: Conference paper submission scheduled for March 2026 (Upcoming)
• ⏳ Repository Public Release: Full design documentation and repository will be made public following publication acceptance (Post-Publication)

Design Visualizations - Not Available

Due to the confidential nature of this project and ongoing publication process, design visualizations including:

• HFSS 3D inductor models and field distributions
• Q-factor vs. frequency plots and optimization curves
• Layout screenshots from Klayout
• Circuit schematic diagrams
• Simulation results and performance data

...cannot be publicly shared at this time. Images and detailed results will be added to this page after the competition concludes and the design is submitted for tapeout.

Key Learnings & Skills Developed

• Fractional-N PLL Architecture: Deep understanding of Type-II Delta-Sigma fractional-N PLL operation, including charge pump dynamics, LC-VCO design principles, frequency dividers, and delta-sigma modulator for fractional frequency synthesis
• RF Inductor Theory for 2.4 GHz: Comprehensive knowledge of spiral inductor operation at 2.4 GHz, Q-factor optimization techniques, substrate loss mechanisms (eddy currents, displacement currents), skin effect, proximity effect, self-resonance, and phase noise contribution in LC-VCO tanks
• HFSS Electromagnetic Simulation Expertise: Advanced proficiency in 3D full-wave EM simulation, adaptive mesh refinement strategies, S-parameter extraction and de-embedding, field visualization (H-field, current density), parametric optimization sweeps, and inductor-specific simulation setup for accurate Q-factor prediction
• IHP SG13G2 PDK Mastery: Hands-on experience with IHP 130nm SiGe BiCMOS PDK layer stackup, design rules, metal stack properties (ThinMet through TopMetal2), via structures, and fabrication constraints specific to BiCMOS technology. Understanding of advantages over CMOS for RF applications (thicker metals, better substrate isolation)
• Novel PVT Analysis Methodology: Developed research-grade methodology for investigating Process-Voltage-Temperature variations impact on passive RF components. Analyzing metal thickness variations (±10-20%), temperature-dependent substrate loss (-40°C to +125°C), and demonstrating PLL lock robustness across fabrication corners - primary research contribution for publication
• SPICE Modeling with Parasitic Extraction: Creating accurate broadband SPICE subcircuit models from HFSS S-parameters, π-model parameter extraction, frequency-dependent R-L-C networks, and generating PVT corner model libraries for Monte Carlo yield analysis
• IC Layout for RF/High-Frequency: Understanding of GDS-II layout techniques for RF passives, ground return path optimization, shielding and guard ring strategies, dummy fill impact on Q-factor, and layout-aware inductor design for minimal parasitic coupling to adjacent PLL blocks
• Phase Noise Analysis: Calculating inductor Q-factor contribution to LC-VCO phase noise, Leeson's equation application, phase noise budgeting for fractional-N PLL, and optimizing inductor Q to meet Bluetooth LE spectral purity requirements
• Cross-Functional Team Collaboration: Working in multidisciplinary RFIC design team, interfacing inductor designs with VCO and charge pump designers, managing shared design resources, participating in weekly design reviews, and coordinating for Sri Lanka's first RFIC tapeout milestone
• Research Publication Process: Preparing technical content for MIXDES 2026 conference submission, documenting novel PVT analysis methodology, creating publication-quality figures and simulation results, and managing intellectual property and confidentiality requirements during active research
• Design Automation & Scripting: Python scripting for parametric HFSS geometry generation, batch simulation management across PVT corners, automated S-parameter post-processing, and data visualization for large parametric sweep datasets
• PDK Transition Management: Experience in evaluating and transitioning between PDKs (SKY130 to IHP SG13G2) based on technical constraints (inductor size limitations, timing issues), re-implementing designs in new technology, and adapting workflows to different foundry design rules

Technical References

• Razavi, B. (2011). RF Microelectronics (2nd ed.). Prentice Hall. - Chapters on fractional-N PLL design, delta-sigma modulation, and LC-VCO phase noise analysis
• Lee, T. H. (2004). The Design of CMOS Radio-Frequency Integrated Circuits (2nd ed.). Cambridge University Press. - Inductor design principles, Q-factor optimization, and PLL frequency synthesizers
• Craninckx, J., & Steyaert, M. S. J. (1997). "A 1.8-GHz Low-Phase-Noise CMOS VCO Using Optimized Hollow Spiral Inductors." IEEE Journal of Solid-State Circuits, 32(5), 736-744. - Inductor optimization for VCO applications
• Mohan, S. S., et al. (1999). "Simple Accurate Expressions for Planar Spiral Inductances." IEEE JSSC, 34(10), 1419-1424. - Foundational inductor modeling formulas and design equations
• Yue, C. P., & Wong, S. S. (1998). "Physical Modeling of Spiral Inductors on Silicon." IEEE Transactions on Electron Devices, 45(3), 560-568. - Substrate coupling and loss mechanisms in silicon inductors
• Riley, T. A. D., et al. (1993). "Delta-Sigma Modulation in Fractional-N Frequency Synthesis." IEEE JSSC, 28(5), 553-559. - Delta-sigma modulator design for fractional-N PLLs
• IHP SG13G2 PDK Documentation - 130nm SiGe BiCMOS Design Manual - Layer stackup, design rules, and metal stack specifications
• Ansys HFSS Documentation - 3D Component Design and Electromagnetic Simulation for RF Passives

Post-Publication Updates

This page will be updated with comprehensive design details, simulation results, layout screenshots, PVT analysis data, and full performance analysis after:

• ✅ MIXDES 2026 Conference paper submission (March 2026)
• ✅ Publication acceptance and conference presentation
• ✅ Tapeout completion and fabrication submission
• ✅ All intellectual property and confidentiality requirements are cleared

What will be shared post-publication:

• Complete HFSS 3D inductor models and field distribution visualizations
• Q-factor vs. frequency plots and parametric optimization curves for 2.4 GHz
• S-parameter datasets and SPICE model generation methodology
• Novel PVT analysis results: process corner simulations, temperature sweeps, and PLL lock robustness data
• Full PLL architecture overview and integration with VCO/charge pump circuits
• Layout screenshots and GDS-II files (if permitted by fabrication agreement)
• Phase noise simulation results and comparison with Bluetooth LE specifications
• GitHub repository with design automation scripts and documentation
• Published conference paper and presentation slides

Thank you for your understanding and interest in Sri Lanka's First RFIC Tapeout! Stay tuned for comprehensive updates showcasing the complete fractional-N PLL design process and novel PVT analysis methodology following MIXDES 2026 publication.