RFIC Inductor Design Workflow

Confidentiality Notice

This is an active research project. Due to ongoing publication process and intellectual property considerations, detailed circuit design, specifications, and simulation results cannot be publicly disclosed at this time. Information will be updated after paper submission and the tapeout is completed.

Project Overview

This is a group RFIC design project that is part of an IC design program that started in 2025, targeting a tapeout in 2026. The project involves designing an RF integrated circuit using the SkyWater SKY130 130nm CMOS PDK, an open-source process design kit.

My Specific Role: Within the group, I am primarily responsible for:

• RFIC Inductor Design Workflow Development: Developing a complete workflow for designing on-chip spiral inductors using Ansys HFSS 3D Layout with SKY130 PDK layer stackup specifications
• Electromagnetic Simulation: Full-wave 3D EM simulation and parametric optimization of inductors
• Future Layout Contribution: May be assigned to IC layout implementation in later project stages

Project Scope (General Information)

While detailed circuit specifications are confidential pending publication, the general project scope includes:

• Technology Node: SkyWater SKY130 130nm CMOS process
• Application: RF integrated circuit design for wireless communication systems
• Design Methodology: Full-custom analog/RF IC design
• Passive Components: Custom-designed on-chip spiral inductors optimized for high Q-factor
• Design Tools: Xschem (schematic), ngspice (simulation), Klayout (layout), HFSS 3D Layout (EM simulation)
• Timeline: Targeting tapeout in 2026 for fabrication through open-source shuttle runs

Current Work: RF Inductor Design in HFSS 3D Layout

My current focus is on developing a complete inductor design workflow using Ansys HFSS 3D Layout. This involves:

SKY130 PDK Layer Stackup Integration

The SKY130 process offers multiple metal layers with specific thickness and spacing specifications. Accurate 3D modeling of the complete layer stackup in HFSS is critical for realistic inductor performance predictions:

• Metal Stack: Modeling all 5 metal layers (M1-M5) with correct thicknesses and dielectric spacing
• Substrate Modeling: Silicon substrate with appropriate doping, thickness, and loss tangent
• Via Structures: Inter-layer vias for connecting inductor turns and ground returns
• Patterned Ground Shields: Optional ground plane shields to reduce substrate losses

Inductor Performance Optimization

Key parameters being optimized through parametric HFSS sweeps:

• Quality Factor (Q): Maximizing Q at the target operating frequency through geometry optimization
• Self-Resonant Frequency (SRF): Ensuring SRF is sufficiently above operating frequency
• Inductance Value: Achieving target inductance (typically 1-10 nH range for RF applications)
• Series Resistance: Minimizing metal loss through optimal trace width and metal layer selection
• Substrate Coupling: Analyzing and mitigating eddy current losses in silicon substrate
• Magnetic Field Distribution: Visualizing H-field to understand coupling to adjacent components

Design Variables & Trade-offs

Design Workflow & Methodology

1. HFSS 3D Layout Electromagnetic Simulation Setup

Creating accurate inductor models in HFSS 3D Layout for SKY130:

• Import PDK Stackup: Define all metal and dielectric layers with exact SKY130 specifications (thicknesses: M1=0.36µm, M2=0.36µm, M3=0.845µm, M4=0.845µm, M5=1.26µm)
• Geometry Creation: Draw spiral inductor patterns with parametric variables (turns, width, spacing, diameter)
• Port Definition: Lumped port excitation at inductor terminals for S-parameter extraction
• Boundary Conditions: Radiation boundary (air box) and perfect E/H boundaries for computational efficiency
• Mesh Generation: Adaptive mesh refinement focused on high-current-density regions
• Frequency Sweep: S-parameter simulation from DC to 20+ GHz to capture SRF and broadband behavior

2. Inductor Performance Extraction

Post-processing HFSS results to extract key inductor metrics:

• Inductance (L): Extracted from Im(Z₁₁) = 2πfL at target frequency
• Quality Factor (Q): Q = Im(Z₁₁) / Re(Z₁₁) = ωL / R_series
• Series Resistance (R_s): Real part of input impedance including skin effect and substrate loss
• Self-Resonant Frequency: Frequency where Im(Z₁₁) = 0 (inductive→capacitive transition)
• Coupling Coefficient (k): For transformer/coupled inductors, k = M / √(L₁L₂)

3. Layout Implementation in Klayout

Translating optimized HFSS geometries into manufacturable IC layouts:

• GDS Export: Generate GDS-II layout files from verified inductor designs
• DRC Compliance: Ensure all design rules are met (minimum width, spacing, enclosure, density)
• LVS Verification: Layout-versus-schematic check for inductor connectivity
• Dummy Fill: Metal density fill patterns to meet foundry requirements without degrading Q
• Guard Rings: Substrate contact rings to minimize noise coupling to/from inductors

4. Integration with Circuit Design

Providing inductor models to the circuit design team:

• S-Parameter Models: Export 2-port S-parameters for use in circuit simulators (ngspice, Spectre)
• Equivalent Circuit Models: Fit HFSS data to π-model or more complex RLC networks
• Performance Tables: Document L, Q, SRF vs. frequency for circuit design reference
• Layout Footprint: Provide physical dimensions and port locations for floorplanning

Tools & Technologies

Project Timeline & Status

• ✅ PDK Selection: Transitioned from IHP PDK to SKY130 based on project requirements
• ✅ HFSS Stackup Setup: Complete SKY130 layer stackup modeled in HFSS with accurate material properties
• 🔄 Inductor Design & Optimization: Parametric sweeps and Q-factor optimization ongoing (Current Phase)
• 🔄 Layout Development: Klayout implementation of optimized inductor geometries (In Progress)
• ⏳ DRC/LVS Verification: Design rule and layout verification (Upcoming)
• ⏳ Full Circuit Integration: Integration of passive components with active circuits (Planned)
• ⏳ Post-Layout Simulation: Extracted parasitic simulation (Upcoming)
• ⏳ Tapeout Submission: Target: 2026 (Planned)

Design Visualizations - Not Available

Due to the confidential nature of this project and ongoing publication process, design visualizations including:

• HFSS 3D inductor models and field distributions
• Q-factor vs. frequency plots and optimization curves
• Layout screenshots from Klayout
• Circuit schematic diagrams
• Simulation results and performance data

...cannot be publicly shared at this time. Images and detailed results will be added to this page after the competition concludes and the design is submitted for tapeout.

Key Learnings & Skills Developed

• RF Inductor Theory: Deep understanding of spiral inductor operation, Q-factor optimization, substrate loss mechanisms, skin effect, proximity effect, and self-resonance phenomena
• HFSS Electromagnetic Simulation: Proficiency in 3D full-wave EM simulation, adaptive mesh refinement, S-parameter extraction, field visualization, and parametric optimization for passive RF components
• SKY130 PDK Expertise: Hands-on experience with open-source PDK layer stackup, design rules, metal stack properties, and fabrication constraints specific to 130nm CMOS technology
• IC Layout for RF: Klayout GDS-II layout techniques, DRC/LVS verification, dummy metal fill strategies, guard ring placement, and RF-aware floorplanning to minimize parasitic coupling
• Trade-off Analysis: Balancing competing inductor requirements (high Q vs. small area, high L vs. high SRF, low R vs. process constraints) for optimal RF circuit performance
• Design Automation: Python scripting for parametric HFSS geometry generation, batch simulation management, and post-processing of large datasets from parametric sweeps
• Team Collaboration: Working in a multidisciplinary team environment, interfacing inductor designs with circuit designers, managing shared resources, and meeting collective competition milestones
• Competition Project Management: Handling confidentiality requirements, organizing documentation for submission, and adapting to evolving project goals (PDK transition from IHP to SKY130)

Technical References

• Razavi, B. (2011). RF Microelectronics (2nd ed.). Prentice Hall. - Chapter on VCO design and LC tank optimization
• Lee, T. H. (2004). The Design of CMOS Radio-Frequency Integrated Circuits (2nd ed.). Cambridge University Press. - Inductor design principles
• Mohan, S. S., et al. (1999). "Simple Accurate Expressions for Planar Spiral Inductances." IEEE JSSC, 34(10), 1419-1424. - Inductor modeling formulas
• SkyWater PDK Documentation: https://skywater-pdk.readthedocs.io/ - Layer stackup and design rules
• Ansys HFSS Documentation - 3D Component Design and Electromagnetic Simulation

Post-Competition Updates

This page will be updated with comprehensive design details, simulation results, layout screenshots, and performance analysis after:

• ✅ Competition submission deadline passes
• ✅ Tapeout is completed (2026 target)
• ✅ All intellectual property and confidentiality requirements are cleared

Thank you for your understanding. Stay tuned for future updates showcasing the complete RFIC design process!